Why Intel Never Caught Up to TSMC—Answer Hidden in the Grand Scribe’s Records and Morris Chang’s Autobiography

Liang-rong Chen

As previewed in our last newsletter, this issue continues the discussion on the possibility of TSMC being forced to acquire Intel, with further in-depth analysis.

I’ve always been curious—why do veteran TSMC engineers show visible disdain whenever Intel’s foundries are mentioned? Upon digging deeper, I discovered that despite both companies possessing the most advanced semiconductor technologies in Asia and the West, their fundamental approaches to manufacturing have been vastly different from the very beginning. Part of the answer can be found in the second volume of Morris Chang’s autobiography. This divergence in philosophy became the key factor in TSMC’s meteoric rise and Intel’s downfall.

One of the earliest recorded applications of game theory can be found in the Grand Scribe’s Records (Shiji，史記), specifically in the biography of Sun Bin and Wu Chi（孫子吳起列傳）: the story of Tian Ji’s horse race.

The military strategist Sun Bin, said to be a descendant of Sun Tzu, taught his employer how to overcome inferior horse quality and win a bet by adopting a “two-out-of-three” strategy. This led to the well-known tactic:

“Use your weakest horse against the opponent’s strongest, your strongest against their medium-tier, and your medium-tier against their weakest.”

This strategic lesson from over two thousand years ago is, in essence, the foundation of TSMC’s competitive advantage today. It also explains why Intel is collapsing, prompting the U.S. government and its board of directors to push for selling its manufacturing business to TSMC.

In 1985, Morris Chang responded to a request from K.T. Li and proposed the pure-play foundry model, founding TSMC. In the second volume of his autobiography, he explicitly states that this was “the semiconductor business model with the highest chance of success, given Taiwan’s conditions at the time.”

So, what were Taiwan’s “conditions” at the time?

A narrow interpretation would focus on the six-inch “demonstration line” at ITRI, which later became TSMC’s Fab 1. This pilot line had an exceptionally high yield rate, suggesting that if the team specialized in contract manufacturing, it could achieve international competitiveness.

Behind this high yield rate was a group of young, highly educated, and hardworking engineers. For example, in my podcast 阿榕伯胡說科技, former TSMC VP Chen Chien-Pang recalled how, at just 32 years old, he became a process manager at TSMC’s first fab. Chen had bachelor’s and master’s degrees in physics from National Taiwan University (NTU) and National Tsing Hua University (NTHU). He was part of a cohort that transferred from ITRI to TSMC, including the current Co-COO of TSMC, Y. P. Chin, who holds a master’s degree in electrical engineering from National Cheng Kung University (NCKU).

Chen recalled that from day one, TSMC prioritized “manufacturing excellence.” Engineers worked up to 80-hour per week, and nearly all production line engineers had master’s degrees. Supervisors were extremely strict—if a machine went down, they would demand: “Why did you stop the machine? Not allowed! We need to keep production going.”

Like Chen and Chin, tens of thousands of highly educated engineers graduated from Taiwan’s top universities each year, willing to endure harsh factory conditions. This broader interpretation of “Taiwan’s conditions” explains how TSMC had the right foundation for its success.

What Morris Chang Learned from Texas Instruments

Before founding TSMC, Morris Chang’s last position at Texas Instruments (TI) was as General Manager of Quality Control.

He was shocked to discover that for the same semiconductor product, TI’s Houston plant had a yield rate of just over 20%, whereas its Tokyo plant achieved 40–50%—almost double.

The key factor? The quality of personnel.

In Japan, semiconductor production lines were staffed by engineers with degrees in “relevant technical fields”, whereas in the U.S., top engineering graduates refused to work in factories, preferring R&D, marketing, or business roles instead.

The same issue applied to equipment engineers. In Japan, top-tier engineers ensured that advanced precision equipment ran at 90% efficiency, whereas in the U.S., the figure was just 50–60%.

Chang wrote that his experience at TI’s Japan division “directly inspired my vision for TSMC.” Even though Taiwan was a semiconductor “backwater” at the time, he believed that by assembling top graduates from NTU, NTHU, NCTU (Now NYCU) and NCKU—his “top-tier horses”—he could build a world-class wafer fab that would outperform those managed by medium- or low-tier engineers in the U.S.

This philosophy became the foundation of TSMC’s early success.

The Intel Problem: Prioritizing R&D Over Manufacturing

Decades later, it became standard for semiconductor fabs to be filled with highly educated engineers. But this led to societal concerns—were national university master’s graduates being “wasted” working night shifts running equipments on production lines?

A former TSMC plant manager scoffed at this notion: “How could it just be running equipments?” He argued that because TSMC has high-caliber engineers, “so our fabs can continuously innovate and improve.” Then, he added: “This is something Intel will never be able to match.”

source: Shutterstock

In the early 2000s, this plant manager visited an Intel factory with industry peers and was shocked—despite Intel’s undisputed technological lead at the time, its factory operations lagged behind TSMC “by multiple levels.”

For instance, at the time TSMC had already fully digitalized its fab management, yet Intel still relied on hand-drawn SPC (Statistical Process Control) charts taped to production control areas—a sign of Intel’s disregard for manufacturing.

The most telling example of Intel’s approach is its well-known “Copy Exactly” methodology.

This model allows Intel to replicate R&D fab processes with precision across all its fabs worldwide, whether in Israel, Ireland, or Dalian, China. This eliminates adaptation issues—unlike TSMC, which must adjust to different environments.

An Intel executive once described Copy Exactly to me with great reverence, explaining that even equipment placement, pipeline angles and height, factory temperature, humidity, and air pressure must be identical to the R&D fab. “Don’t underestimate how much effort goes into those two words,” he said.

But to former TSMC manufacturing leaders, this model highlighted Intel’s deep-seated organizational bias toward R&D over manufacturing.

“Intel’s R&D teams have always seen manufacturing as something for fools. They think factories should just follow orders—no need for change and independent thinking.”

This rigid system became Intel’s Achilles’ heel when it entered sub-10nm process nodes. “The challenge of entering the leading edge process is approaching the physical limits, requiring extreme precision—something Intel’s segregated structure couldn’t accommodate.”

Intel’s EUV Struggles vs. TSMC’s Mastery

In Intel’s January earnings call, it revealed that in 2024, chips produced using Extreme Ultraviolet Lithography (EUV) accounted for only “over 5%” of its wafer revenue.

An analyst told me, “That number was shocking. It means Intel bought a ton of EUV machines but can’t use them effectively.”

The numbers reveal a brutal reality—although Intel claims to have ramped up production of 4nm and 3nm chips, obviously their actual volumes remain very low. To sustain operations, Intel has had to rely on older 7nm and 10nm nodes, which do not require EUV technology.

This stark contrast with TSMC, whose sub-7nm revenue share (almost entirely EUV-based) has surpassed 70%, highlights Intel’s ongoing struggles.

There are many theories behind Intel’s rapid collapse—some blame non-technical CEOs, others point to arrogance or internal power struggles.

But to TSMC veterans, there’s only one explanation: Intel’s long-standing neglect of manufacturing has finally caught up with it.

One former TSMC fab director posed a simple question: “Why was Intel’s 10nm delayed for so long (four years)?”

He believes that because Intel’s R&D team could never get the yield rate high enough for mass production, leading to delay after delay.

If it were TSMC, once R&D reaches a certain stage, the process would be transferred to the manufacturing side for mass production preparation.

Since TSMC’s fab engineers and headquarters R&D personnel have similar levels of expertise, process development does not occur in isolation. When development reaches its midway point, process integration engineers from the factory will be stationed at the Hsinchu R&D production line for on-site training while providing feedback. These engineers will then transfer the technology back to the fabs for mass production, continuously refining the process, identifying issues, and making necessary adjustments.

However, Intel cannot operate this way. It must perfect the R&D phase before transferring it to the fabs, because “otherwise, the fabs would not be able to handle it. They have only ever known how to copy,” said a former TSMC fab director.

This former plant manager expressed pride that TSMC engineers are constantly engaged in “independent research and continuous improvement”—from fab facility systems to equipment and operational environments, everything undergoes constant optimization. As a result, the cost per unit of production can be reduced to half of what it was at the initial stage of mass production.

"This is a one-way version of 'Copy Exactly'—Intel will never catch up," he concluded.

It is no surprise, then, that when I asked this veteran TSMC engineer what would happen if TSMC were to take over all of Intel’s fabs, his response was immediate:

"Absolutely impossible."

He shook his head and explained that the management systems and cultures of both companies are fundamentally different. The only way would be to “tear everything down and start over from scratch." But he added, "with tens of thousands of employees still there, how could we possibly start over?"

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